1. Field of the Invention
The present invention relates to a capacitance measurement method using a CBCM (Charge Based Capacitance Measurement) circuit.
2. Description of the Background Art
(Basic Principle of CBCM Technique)
A CBCM technique is a method for measuring capacitance values on a sub-fF level (xe2x89xa610xe2x88x9215 F) that cannot be measured with sufficient accuracy by AC measurement equipment such as an LCR meter.
FIG. 7 is a circuit diagram illustrating a configuration of a CBCM circuit adopting a conventional CBCM technique. As shown, a PMOS transistor MP1 and an NMOS transistor MN1 are connected in series, and a PMOS transistor MP2 and an NMOS transistor MN2 are connected in series. The source of the PMOS transistor MP1 is connected to a power pad 52, the source of the PMOS transistor MP2 is connected to a power pad 54, and the sources of the NMOS transistors MN1 and MN2 are connected in common to ground level. A PMOS gate potential Gp is applied to the gates of the PMOS transistors MP1 and MP2, while an NMOS gate potential Gn is applied to the gates of the NMOS transistors MN1 and MN2.
A reference capacitance Cref (reference value=Cm (dummy capacitance)) is provided between drain (node N1) and source of the NMOS transistor MN1, and a test capacitance Ctst (capacitance value=Cm+Ct (target capacitance)) is provided between drain (node N2) and source of the NMOS transistor MN2. The purpose of the CBCM circuit shown in FIG. 7 is to measure the target capacitance Ct.
FIG. 8 is a timing chart illustrating the operation of the CBCM circuit shown in FIG. 7. Hereinbelow, with reference to this drawing, capacitance measurement by the conventional CBCM circuit will be described.
As shown, input voltage waveforms of the PMOS gate potential Gp and the NMOS gate potential Gn are such that at least either the NMOS transistors MN1, MN2 or the PMOS transistors MP1, MP2 are in the off state at any given time. Thus, no short circuit current flows from the PMOS transistor MP1 to the NMOS transistor MN1 or from the PMOS transistor MP2 to the NMOS transistor MN2.
As shown in FIG. 8, during a time interval between t1 and t2, the PMOS transistors MP1 and MP2 are turned on to supply currents Ir and It from the power pads 52 and 54 and thereby to charge the reference capacitance Cref and the test capacitance Ctst. During this time, the NMOS transistors MN1 and MN2 are both in the off state and thus, potentials at the nodes N1 and N2 which are connected respectively to the reference capacitance Cref and the test capacitance Ctst reach a power supply potential Vdd.
During a time interval between t2 and t3, the PMOS transistors MP1, MP2 and the NMOS transistors MN1, MN2 are all in the off state. Ideally, the accumulated charges on the reference capacitance Cref and the test capacitance Ctst should be stored and the nodes N1 and N2 should be maintained at the power supply potential Vdd.
During a time interval between t3 and t4, only the NMOS transistors MN1 and MN2 are in the on state. Thus, the accumulated charges on the reference capacitance Cref and the test capacitance Ctst are discharged to ground level and the potentials at the nodes N1 and N2 reach a ground potential Vss.
During a time interval between t4 and t5, all the MOS transistors are in the off state. Ideally, the reference capacitance Cref and the test capacitance Ctst should be maintained at the ground potential Vss since the completion of discharge.
These are one cycle T of operation (the time from t1 to t5) and hereinafter, this operation will be repeated. To be observed by the measurement equipment is average values of the currents Ir and It with respect to time. Where f(=1/T) is the frequency of the gate input waveforms (Gp, Gn), the target capacitance value Ct can be obtained from the following equations (1) and (2).
IC=Itxe2x88x92Irxe2x80x83xe2x80x83(1) 
                              C          t                =                                            C              tst                        -                          C              m                                =                                    I              C                                                      V                dd                            ·              f                                                          (        2        )            
The advantage of the CBCM technique is that, as expressed in Equations (1) and (2), the dummy capacitance (parasitic capacitance) Cm can be cancelled and a desired target capacitance Ct can be obtained.
In this way, the CBCM technique allows measurement of capacitance values. In the capacitance measurement technique using the CBCM circuit, however, if there is leakage of charge from the test resistance Ctst and the amount of leakage cannot be ignored as compared with the amount of charging current (e.g., 1% or more as a current value), treating the observed current It as a charging current will cause an error of the measured capacitance value.
FIG. 9 is a circuit diagram showing an equivalent circuit on the side of the test capacitance Ctst, where there is no leakage current. As shown, if there is no leakage current, the circuit configuration is equivalent to that in which the test capacitance Ctst and a resistance Rs (such as a transistor""s resistance) are connected in series.
FIG. 10 is a circuit diagram showing an equivalent circuit on the side of the test capacitance Ctst, where there is a leakage current. As shown, if there is a leakage current, the circuit configuration is such that a resistance Rt is additionally connected parallel to the test capacitance Ctst.
FIG. 11 is a circuit diagram showing an equivalent circuit of the CBCM circuit when there is a leakage current. As shown, the circuit configuration shown in FIG. 10 is connected between drain and source of the NMOS transistor MN2, and the current It supplied from the power pad 54 flows as a current ICt through the test capacitance Ctst and flows as a current IRt through the resistance Rt.
FIG. 12 is an explanatory diagram for indicating a problem of the leakage current. As shown, even during the period in which the PMOS transistor MP1 is in the on state with the application of the PMOS gate potential Gp (i.e., during the period in which the NMOS transistor MN1 should be in the off state), the current IRt will flow as a leakage current.
Capacitance measurement (extraction) using the conventional CBCM technique assumes that currents observed on the side of power supply potential Vdd are all used for charging the MOS transistors forming the CBCM circuit, the test capacitance Ctst, and the dummy capacitance Cm. Thus, if there is a leakage current, even a charge which actually corresponds to a leakage current flowing through the resistance Rt is treated as an accumulated charge, which causes a problem that the measured capacitance value may become larger than the actual capacitance value.
An object of the present invention is to provide a capacitance measurement method which is capable of measuring an accurate capacitance value even if a leakage current on a level that cannot be ignored occurs in a capacitance to be measured.
According to the present invention, the capacitance measurement method is for measuring a capacitance to be measured which is connected to a CBCM (Charge Based Capacitance Measurement) circuit including a charge transistor, and includes the following steps (a) to (e). The step (a) is to apply to the charge transistor a first control signal for controlling turning on/off of the charge transistor in a predetermined cycle, thereby to measure an amount of first test current to be supplied through the charge transistor to the capacitance to be measured. The step (b) is to apply to the charge transistor a second control signal for controlling turning on/off of the charge transistor in the predetermined cycle, thereby to measure an amount of second test current to be supplied through the charge transistor to the capacitance to be measured. A period during which the second control signal indicates an on state of the charge transistor is set to be predetermined times longer than that during which the first control signal indicates an on state of the charge transistor. The step (c) is to, based on the first and second test currents, eliminate a leakage current occurring incident to the capacitance to be measured and calculate an amount of capacity current used only for charging the capacitance to be measured. The step (d) is to calculate a charge frequency suitable for the amount of capacity current. The step (e) is to calculate a capacitance value of the capacitance to be measured based on the amount of capacity current and the charge frequency.
The amounts of the first and second test currents measured by the execution of the above steps (a) and (b) each are equal to the sum of the amounts of capacity current and leakage current. The second test current has the same amount of capacity current as the first test current, but has a predetermined times larger amount of leakage current. Thus, in step (c), the amount of the first test current is increased by the predetermined times and operations such as obtaining a difference from the amount of the second test current is performed, whereby an accurate amount of capacity current used only for charging the capacitance to be measured can be calculated. Consequently, by the execution of the subsequent steps (d) and (e), it is possible to calculate an accurate capacitance value of the capacitance to be measured, from which a leakage current occurring incident to the capacitance to be measured has been eliminated.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.